1. Field of the Invention
The invention relatives to a semiconductor processing method, and more particularly to a fabrication method for forming a shallow isolation trench with global planarization on a semiconductor substrate.
2. Background of the Invention
With the advent of millions of electronic components integrated on a single chip, proper electrical isolation of the components becomes critical. It is well known that if the isolation of electrical elements is poor, boring leakage will occur, and the accumulated leakage of millions of electrical elements can result in latch up which is likely to damage the circuit and, obviously manifest itself in observable wasted power consumption. Further, such leakage affects the circuit's noise-resistance, resulting in voltage displacement and cross-talk.
In the fabrication of semiconductor ICs, there are several issues of importance such as isolation planarity, isolation depth, and abrupt transitions between active areas and isolation areas. In an IC, SiO.sub.2 is typically used as the isolation layer (or isolation trench). Therefore, to produce high quality semiconductor ICs, it is crucial to effectively control the growth and characteristics of isolation layers.
Local Oxidation of Silicon (LOCOS) is a commonly employed method of forming an isolation trench. This method utilizes a mask formed by, for example, a silicon nitride film and a pad oxide to grow the SiO.sub.2 isolated trench on a specific region of the chip. However, since the volume of the SiO.sub.2 is as twice that of silicon, and adding the effect of lateral oxidation, a so-called bird's beak encroachment is typically formed on the two sides of the isolation trench, which will reduce the active area and shorten the channel length of the active electrical element. This results in not only deterioration of the integrated circuits but also impediments to VLSI fabrication.
In conventional approaches to the problem, such as Side Wall Masked Isolation (SWAMI), and Sealed Interface Local oxidation, etc., although avoiding some bird's beak encroachment, these processes involved are typically extremely complicated.
In other processing technology for achieving shallow trench isolation, a major step involves using plasma etching to etch the substrate to 200 nm depth and the selection of an appropriate dielectric material to fill the trench. Refer to "Characteristic of CMOS Device Isolation for the VLSI Age" in IEDN, p.671, 1994 by Bryant, et al. Although limiting the bird's beak lateral encroachment, plasma etching is apt to result in defects in the wafer and in charge leakage. In addition, this process would likely reduce the active area and shorten the channel width of the active elements.